As it is known in the art, often a computing system is assembled from several functional units which operate together to perform a given task as quickly as possible. Often functional units which exchange data may be operating at different clocking frequencies, for example a Central Processing Unit (CPU) may operate at a faster clocking frequency, or cycle time, than an Input/Output (I/O) unit.
In order to ensure that a valid data transfer occurs, a common frequency for the two functional units is generally derived. For example, if a given CPU unit has a cycle time of 40 ns, and a given I/O unit has a cycle time of 50 ns, then the easiest obtainable cycle time is 200 ns. Once the common frequency has been selected, each of the two clocks periods is multiplied by the appropriate number to provide two clock signals which are operating at the same frequency.
Although both the CPU and the I/O unit may be operating at the same frequency, they may not be phase matched, and data may not be accurately transferred between the two functional units. To ensure accurate data transfer, a common method of phase matching clocks is through the use of a phase locked loop.
Typically in phase locked loop designs, one clocking signal is provided as a reference clock, and the relative phase of the second clocking signal with respect to the reference clock signal is adjusted until both clock signals are in phase. The phase locked loop allows the two clocking signals to remain in phase during operation despite variances in the reference clocking signal due to temperature changes, etc, and thus data transfer between the two functional units is ensured throughout operation.
The reference clock signal on one functional unit is typically driven by a fixed oscillator. The adjusted clocking signal is typically provided by a variable frequency oscillator, for example a voltage controlled oscillator. As discussed previously, the two clock signals may have different clocking frequencies, and therefore a phase locked loop may include a divider circuit for each clock signal to adjust each of the clocking frequencies to a common frequency.
A phase detector circuit is used in the phased lock loop to compare the phase of the reference clock signal to the phase of the adjusted clocking signal and to provide an error signal to adjust the phase of the voltage controlled oscillator. One type of phase detector is a three state phase detector which detects a rising edge of each clocking signal. Two signals are provided from the three state phase detector, one signal which is a reference clock detect signal and one signal which is the adjustable frequency detection signal. Each detection signal is asserted when the respective clock signal is asserted, and remains asserted until both clock signals are asserted. Thus, each detection signal is basically a train of pulses, with the width of each pulse in the train of pulses indicative of the phase difference between the two clocking signals. The reference detection signal and the adjustable frequency detection signal are fed to a low pass filter to remove the reference clock signal. The filter provides the error signal as a voltage level to the voltage controlled oscillator with the voltage level being related to the phase error between the reference clock signal and the adjustable clock signal.
One problem with the above mentioned phase detector occurs when the common frequency which is provided has a relatively low frequency compared to the frequency of the reference and variable clock signals. As the common frequency decreases, the timing error, or skew, between synchronized clock edges increases. A low timing error, or skew, is desired between the corresponding pulses of the two clock signals to reduce noise in the clock signals. Lower noise levels permit logic designs having longer propagation delay chains to be provided between clock edges. The timing error between the clock signals is related to the characteristics of the phase detector. In particular the timing error is related to the phase error as shown by the below equation: EQU T.sub.E =.phi..sub.E /F.sub.D
where:
T.sub.E is the timing error, or skew, between relative clock pulses PA0 .phi..sub.E is the phase error provided by the phase detector PA0 F.sub.D is the frequency of the detection pulses provided by the phase detector
One problem, as can be noted from the above equations and discussions of the origin of the detection pulses, as the common frequency decreases, the timing error is increased due to the concomitant decreasing frequency of the detection pulse train. Moreover, the reference frequency components of the detection pulse train from the phase detector circuit should be filtered out prior to being provided to the voltage controlled oscillator. As the reference frequency decreases the task of low pass filtering becomes more complex due to the effect of the filter's phase response on the phase locked loop performance. Filtering of low frequency digital signals is generally difficult, requiring complex filtering circuits to remove the low frequency components.
To overcome this problem, logic designers typically design logic circuits with fewer levels of logic provided between clocked devices thus allowing for and compensating for higher levels of clock skew. This approach, while ensuring data transfer, is nonetheless undesirable since it typically increases the size of the logic circuit, the number of synchronous levels in the circuit and hence the latency period for transferring data through the circuit.